A is constructed by connecting four Full Adders in series.

• The carry output from each Full Adder is connected to the carry input of the next stage.
• The first Full Adder takes the external C_in as its carry input.
• The final carry output is available at C_out.

Block Diagram

(Each Full Adder passes carry to the next Full Adder, causing a "ripple" effect. This introduces significant latency.)

Verilog Implementation

module RCA4(A, B, C_in, Sum, C_out);
input  [3:0] A, B;
input        C_in;
output [3:0] Sum;
output       C_out;

wire C_0, C_1, C_2;

// Instantiate 4 Full Adders in series
FA FA1 (
    .A(A[0]),
    .B(B[0]),
    .C_in(C_in),
    .Sum(Sum[0]),
    .C_out(C_0)   // Corrected from C-out to C_out
);

FA FA2 (
    .A(A[1]),
    .B(B[1]),
    .C_in(C_0),
    .Sum(Sum[1]),
    .C_out(C_1)
);

FA FA3 (
    .A(A[2]),
    .B(B[2]),
    .C_in(C_1),
    .Sum(Sum[2]),
    .C_out(C_2)
);

FA FA4 (
    .A(A[3]),
    .B(B[3]),
    .C_in(C_2),
    .Sum(Sum[3]),
    .C_out(C_out)
);

endmodule